instruction (Total 19082 Patents Found)

A superscalar microprocessor is provided which includes a integer functional unit and a floating point functional unit that share a high performance main data processing bus. The integer unit and the floating point unit also share a common reorder buffer, register file, branch prediction unit and load/store unit which ...
The invention relates to a computer system and method for fetching a next instruction. In one embodiment, a computer system includes an instruction cache, a next fetch address register, and a fetch unit. The instruction cache includes an instruction array for storing a plurality of processor instructions and a next add...
In an information processing apparatus, an instruction read inhibit bit is provided for branch instruction address and target instruction address registered in pair in the branch history. When the reading of a target instruction predicted from the pair of addresses is inhibited, the instruction read inhibit bit is set ...
A microprocessor has on-chip hardware for protecting software against unauthorized use. The microprocessor includes a decoder for deciphering software instruction codes prior to their execution by the microprocessor. The instruction codes are enciphered in a unique way so that they can only be executed by the specific ...
A program-controlling processing unit executes instructions stored in memory. A special instruction type is provided for selectively retrieving an element from memory in dependence on the value of input data subject of the instruction. Each instruction of this type has a header identifying the instruction type, and a b...
A method for debugging a multi-core microprocessor includes causing the microprocessor to perform an actual execution of instructions and obtaining from the microprocessor heartbeat information that specifies an actual execution sequence of the instructions by the plurality of cores relative to one another, commanding ...
THE ARRANGEMENT OF INSTRUCTIONAL MATERIAL IN EDUCATIONAL TEXTS, FILMS, FILMSTRIPS OR OTHER SIMILAR MEANS OF CUMMUNITATIONS FOR TEACHING GROUPS OF LEARNERS IN WHICH INDIVIDUAL LEARNERS ARE DISTINGUISHED BY DIFFERENT LEARNING ABILITY WITH THE COMMUNICATION MEANS BEING DIVIDED INTO COMPOSITE LEARNING FRAMES HAVING A PLURA...
A data processing apparatus 10 for executing an access instruction for n threads in order to access data values for the n threads includes storage circuitry 100 that stores data values associated with the n threads in groups defined by storage boundaries. The data processing apparatus also includes processing circu...
In an Internet fax, to receive an electronic mail document for fax transfer, if a password related to a control command for indicating a facsimile communication function is encrypted and set in the destination field or the main body of the received electronic mail, the encrypted password is decrypted and using the decr...
A microprocessor architecture comprises an instruction decoding network for decoding in a first mode partially suppressed opcodes of a sequence of instructions, the opcodes comprising a first part containing parameters being invariant for each opcode of the sequence and a second part comprising a flag indicating an end...
L'invention concerne un procédé de fonctionnement d'un processeur consistant à concaténer des premier et second mots en vue de produire un résultat intermédiaire, déplacer ledit résultat d'une quantité de déplacement spécifique et stocker le résultat intermédiaire déplacé dans un troisième m...
L'invention concerne un système de calcul pour l'exécution d'une instruction de symbole de décodage binaire H.264 comprenant une première unité de calcul ayant un circuit de normalisation de plage et un circuit de mise à jour rLPS, et fonctionnant dans un premier mode en réponse en un rLPS courant, u...
De manière à exécuter correctement une fonction par une pluralité de mots, un serveur d'instruction d'exécution de fonction (10) d'un système d'instruction d'exécution de fonction (1) selon l'invention comprend : une unité d'instruction d'exécution de fonction (11) qui ordonne l...
A digital signal processor (10) for implementing a gain instruction. The gain instruction, when decoded, controls a multiplexer (43) to select a gain control index signal. The value of the chosen gain control index signal is added to a program control register (48) to produce a program address. The program address is u...
A computing system includes an application object, a computer based training instruction object ("INSTRUCTION object") and an agent engine. The INSTRUCTION object runs concurrently with the application object. The application objects includes a first action processor and a first command processor. The first act...
A software compiler having a code generator and a scheduler. The code generator transforms a lowered intermediate representation (IR) of a source computer program, written in a known computer language, to an assembly language program written in a non-standard instruction set. In particular, the code generator translate...
An instruction cache having a pattern detector for use in predicting the length of variable length instructions in a microprocessor. The instruction cache comprises an instruction length calculation unit and the pattern detector. The pattern detector is configured with a content addressable memory and update logic. The...
Instruction issue logic is disclosed that assesses register availability. The issue logic comprises register scoreboard logic that includes destination register storage elements to identify destination registers of instructions queued for issue. An arbiter selects instructions for issue during a machine cycle from the ...
In a computer capable of executing a superscalar and a very long instruction word instruction wherein the computer has compiled a number of primitive operations that can be executed in parallel into a single instruction having multiple parcels and each of the parcels correspond to an operation, the invention is an impr...
A method utilizes a register file of an execution unit as a local instruction loop buffer to enable suitable algorithms, such as DSP algorithms, to be fetched and executed directly within the execution unit, and often enabling other logic circuits utilized for other, general purpose workloads to either be powered down ...
A processor includes a core with logic to execute a translated instruction. The translated instruction is translated from an instruction stored in a memory location. The processor further includes a translation lookaside buffer including logic to store translation indicators from a physical map. Each translation indica...
Preventing hazard flushes in an instruction sequencing unit of a multi-slice processor including receiving a load instruction in a load reorder queue, wherein the load instruction is an instruction to load data from a memory location; subsequent to receiving the load instruction, receiving a store instruction in a stor...
A computer readable medium storing a program causing a computer to execute a process for controlling a printing process, the process including: receiving instruction information including (i) a content of the printing process for printing image data and (ii) identification information of an instruction user instructing...
An instruction execution pipeline for use in a data processor. The instruction execution pipeline comprises: 1) an instruction fetch stage; 2) a decode stage; 3) an execution stage; and 4) a write-back stage. The instruction pipeline repetitively executes a loop of instructions by fetching and decoding a first instruct...
In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communication between these reso...
A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key genera...
A method includes, in a processor, processing program code that includes memory-access instructions, wherein at least some of the memory-access instructions include symbolic expressions that specify memory addresses in an external memory in terms of one or more register names. At least a store instruction and a subsequ...
In a multithread processor capable of executing a plurality of threads, in order to select a thread and instruction for increasing a throughput of the multithread processor, an instruction-issuance controlling device included in the multithread processor includes a resource management unit configured to manage stall in...
The present invention is directed to system for and methods of real time observing, monitoring, and detecting anomalies in programs' behavior at instruction level. The hardware assist design in this invention provides fine grained observability, and controllability. Fine grained observability provides unprecedented...
Instruction set techniques have been developed to identify explicitly the beginning of a loop body and to code a conditional loop-end in ways that allow a processor implementation to efficiently manage an instruction fetch buffer and/or entries in an instruction cache. In particular, for some computations and processor...
A processor core supports execution of program instruction from both a first instruction set and a second instruction set. An architectural register file 18 containing architectural registers is shared by the two instruction sets. The two instruction sets employ logical register specifiers which for at least some val...
A method for pseudo-randomly, without bias, selecting instructions for marking in a microprocessor. Responsive to reading an instruction from an instruction cache, an instruction tag associated with the instruction is compared against a pseudo-randomly generated value in a linear feedback shift register (LFSR). If the ...
A system and method for adding reconfigurable computational instructions to a reduced instruction set computer. A computer program contains instruction extensions not native to the instruction set of the processor core and is loaded into an instruction memory accessible by the processor core of the computer. The comput...
An RISC processor and a method for converting and looking-up instruction address in the RISC processor. The device comprises a decoder, which includes a look-up table module for realizing the conversion from an X86 source instruction address to an MIPS target instruction address by using a look-up table. The look-up ta...
Systems and methods are provided through which compare instructions in computer code are eliminated partially resolving the predicate of the compare instructions. Partially resolved predicates are used to reduce the number of compares generated during the prediction phase of the compiler. In a partially resolved predic...
A superscalar microprocessor employing an instruction scanning unit is disclosed. The instruction scanning unit processes start and end byte information associated with a plurality of contiguous instruction bytes. The processing of start byte information and end byte information is performed independently and in parall...
An instruction code is received by an instruction input section 103 and then decoded by the instruction decode section 105 to generate an operand and control signals. The instruction division control section 109 generates a division control signal based on the control signals and an operand selection section 107 genera...
An instruction cache system includes an instruction-cache data storage unit that stores cache data per index, and an instruction cache controller that compresses and writes the cache data in the instruction-cache data storage unit, and controls a compression ratio of the written cache data. The instruction cache contro...
A memory card ( 1 ) includes an electrically rewritable non-volatile memory ( 4 ), a data processor ( 3 ) having a function of executing instructions, and managing the allocation of file data in the non-volatile memory, an interface control circuit ( 2 ) having a function of establishing an external interface, for cont...
A priority circuit is connected to a reservation station and a plurality of arithmetic units that processes different operations and dispatches, when it is determined that an executable flag indicating that an instruction can be executed by only a specific arithmetic unit is on, an instruction to an arithmetic unit tha...
A method, system and computer program product for instruction fetching within a processor instruction unit, utilizing a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. During instruction fetch, modified instruction buffers coupled to an instruction cache (I-cache) temporarily store instruct...